Návod k obsluze mikrokontroléru VECTOR VX1000 ARM TPIU Trace

The VX1000 ARM TPIU Trace is a tool used for measurement and
calibration setups of microcontrollers. It provides a parallel
trace port with single- or multi-pin data paths and a clock pin.
All signals are single-ended.

TPIU Trace Overview:

The TPIU Trace Interface consists of a parallel trace port with
various pins including Trace Clock and Data Pins 0-3. The Trace
Clock typically operates at frequencies ranging from 25 MHz to 125
MHz, with data pins using DDR signaling for increased data
sazby.

TPIU Trace Protocols:

To enable the TPIU Trace, configuration within the ECU software
is necessary. This includes pin configuration, multiplexer
configurations, and trace clock configuration. Detailed
instructions for these configurations can be found in the user
manuál.

Návod k použití produktu:

1. Setting up TPIU Trace:

To use the TPIU Trace Interface, follow these steps:

Connect the TPIU Trace pins according to the specified pin
úkoly.
Configure the ECU software settings for the Trace Pins
interface as per VXconfig settings.

2. Pin Configuration:

Configure the trace data pins and clock pin based on the target
controller specifications. Refer to the provided code examples pro
pomoc.

3. Multiplexer Configurations:

If your evaluation board or ECU has multiplexers or DIP
switches, ensure they are configured to select the TPIU-Trace.
Viz kód examples for different evaluation boards.

4. Trace Clock Configuration:

Set up the Trace Clock frequency by selecting the appropriate
clock source and setting a divider to achieve the desired
frequency. Refer to the user manual for detailed instructions.

FAQ:

Q: Where can I find code examples for pin configuration for
different target controllers?

A: Code examples for pin configuration can be found in section 4
of the user manual titled “Code Examples for TPIU
Konfigurace."

Q: How do I configure the Trace Clock frequency?

A: Instructions for configuring the Trace Clock frequency can be
found in section 2.3 of the user manual under “Trace Clock
konfigurace."

“`

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VX1000 ARM TPIU Trace
Verze 1.0 2025-08-29 Aplikační poznámka AN-IMC-1-502

Omezení autora Abstrakt

Gunreben, Dominik
Veřejný dokument
Describes all necessary steps to use the TPIU/Trace-Pin Interface of a microcontroller for VX1000 measurement and calibration setups.

1 VX1000 ARM TPIU Trace ………………………………………………………………………………………………..2 1.1 TPIU Trace Overview……………………………………………………………………………………………..2 1.2 TPIU Trace Protocols……………………………………………………………………………………………..3
2 ECU software configuration ……………………………………………………………………………………………3 2.1 Pin configuration ……………………………………………………………………………………………………3 2.2 Multiplexer configurations ……………………………………………………………………………………….3 2.3 Trace Clock configuration ……………………………………………………………………………………….3 2.3.1 Use VX1000 defaults ……………………………………………………………………………………………..4 2.3.2 VXconfig settings …………………………………………………………………………………………………..4 2.3.3 Use ECU settings…………………………………………………………………………………………………..4 2.4 VX1000 Application Driver configuration …………………………………………………………………..5
3 Performance considerations…………………………………………………………………………………………..6 3.1 Target Interface Bandwidth……………………………………………………………………………………..6 3.1.1 Due to the number of different setups, the following table provides an overview of actual target interface bandwidth. Bandwidth Examples of STM500 ………………………………………………..6 3.2 Stalling …………………………………………………………………………………………………………………6
4 Kód Přamples for TPIU Configuration…………………………………………………………………………..7 4.1 Texas Instruments………………………………………………………………………………………………….7 4.1.1 AM263………………………………………………………………………………………………………………….7 4.1.2 J6E ………………………………………………………………………………………………………………………8 4.1.3 TDA4M/J721E……………………………………………………………………………………………………….9
5 VX1000 hardware adaptation ………………………………………………………………………………………..11 5.1 Voltage levels ………………………………………………………………………………………………………11 5.2 Flat Ribbon cables ……………………………………………………………………………………………….11 5.3 Customized Flex PCB …………………………………………………………………………………………..11 5.4 Typical connector used for TPIU Trace …………………………………………………………………..12 5.4.1 ARM Coresight 20………………………………………………………………………………………………..12 5.4.2 ARM Mictor 38 …………………………………………………………………………………………………….12 5.4.3 ARM MIPI60 ………………………………………………………………………………………………………..13 5.4.4 Vector “Coresight 44” ……………………………………………………………………………………………14 5.5 Vector Adapter …………………………………………………………………………………………………….15 5.5.1 VX1940.10: Mipi 60 Adapter ………………………………………………………………………………….15 5.5.2 VX1940.11: Mictor 38 Adapter ……………………………………………………………………………….16 5.6 Vector EEK Heads ……………………………………………………………………………………………….16 5.6.1 VX1902.09 EEK Head ………………………………………………………………………………………….16 5.7 Vector Flex Adapter ……………………………………………………………………………………………..16 5.8 Possible TPIU Setups …………………………………………………………………………………………..17 5.8.1 Setups for VX1453 ……………………………………………………………………………………………….17
6 Contacts ………………………………………………………………………………………………………………………18

VX1000 ARM TPIU Trace
1 VX1000 ARM TPIU Trace
ARM specifies a parallel target interface for its microcontrollers. Depending on the frequency and the number of trace pins used, a significant measurement bandwidth can be achieved with the TPIU Trace Interface. Sometimes the TPIU trace is also referred to as Trace-Pin-Interface or ETM-Trace-Interface. The TPIU Interface is a unidirectional interface from the target controller to the Debugger/Measurement Hardware. The TPIU Interface cannot be used standalone but an additional target interface like SWD or JTAG is required for write accesses to the target.

1.1 TPIU Trace Overview
The TPIU Trace Interface provides a parallel trace port with a single- or multi-pin data path and a clock pin. All signals are single ended.

CoreSight 20 connector Pin

Kolík

CoreSight 20 connector

VTREF

TMS/SWDIO

GND

TCK/SWDCLK

GND

TDO/SWO

Klíč

TDI

GND

nRESET

GND*

TRACECLK

GND*

SLEDOVÁNO0

GND

SLEDOVÁNO1

GND

SLEDOVÁNO2

GND

SLEDOVÁNO3

Figure 1: ARM Coresight 20 Pin assignment

TraceCLK: Trace Clock. Typical frequencies are 25 MHz .. 125 MHz. The TraceDx use DDR signaling, transferring data on both clock edges to double the effective data rate. So when in this document a Trace Clock frequency of 25 MHz is used, the data rate on each data pin is 50 Mbit/s.
TraceD0-TraceD3: Data Pins 0..3. If other target interface connectors are used even more Trace Data Pins can be used if this is supported by the target controller (see 5.4 Typical connector used for TPIU Trace)

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VX1000 ARM TPIU Trace
1.2 TPIU Trace Protocols
The protocols used on the interface may differ depending on the target controller and the use cases. Typically, the TPIU Protocol is used as a container format for multiple data streams. Data streams wrapped in the TPIU protocol can be ARM protocols like Embedded Trace Macrocell (ETM), Instrumentation Trace Macrocell (ITM) or System Trace Macrocell (STM). The VX1000 hardware can decode the TPIU and encapsulated protocols on the fly. VX1000 and the VX1000 Application Driver use ETM, ITM and STM to acquire measurement data efficiently.
2 ECU software configuration
To enable the TPIU Trace, some configuration within the ECU software must be done.
Hint: The VXconfig settings for the Trace Pins interface, which are referenced in the following sections, can be found in VXconfig VX1000 device->POD->Trace Pins

2.1 Konfigurace kolíků
Typically, there are no dedicated trace pins on the target controller, but the trace functionality is multiplexed with other peripheral functionalities on the same pin. To reduce the chance that trace cannot be used as some required pins are blocked by other functionalities, the same trace-pin functionality is often routed redundantly to different pin groups. To enable trace, the target controller must be configured to provide pins with trace functionality and the target PCB must be designed accordingly .
Kód examples for pin configuration for different target controllers can be found in “4. Code Examples for TPIU Configuration”.
These trace pins include the trace data pins (Trace_Data) and the Clock (Trace_Clk) pin. The supported number of trace data pins for the different VX1000 hardware can be found in 5.8 Possible TPIU Setups.
2.2 Multiplexer configurations
If your evaluation board or ECU has multiplexers or DIP switches outside the controller to switch between different peripheral connections, those must be configured as well to select the TPIU-Trace.
See “4. Code Examples for TPIU Configuration” for examples of different evaluation boards.
2.3 Trace Clock configuration
Besides the Trace-Clock pin configuration addressed in “2.1 Pin configuration”, the Trace_Clk must be configured to operate at the desired frequency. Typically, the clock tree contains a multiplexer to select from different clock sources, and frequency dividers to decrease the source frequency. Select the clock source and set a divider to achieve the desired frequency.
To verify the TPIU Clock configuration the VX1000 system measures the detected Trace_Clk signal and shows the result in VXconfig. The values are updated on VX1000 reset, or ECU reset. So, there is no need to connect an Oscilloscope to double check the TPIU frequency.

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VX1000 ARM TPIU Trace

The VX1000 provides three ways to configure the TPIU Clock, which are described in the following sections. The registers that are configured for TPIU Clock MUX and Divider are explained in “4. Code Examples for TPIU Configuration” for the specific controllers. Either the VX1000 hardware can configure the registers from the outside through JTAG/SWD (see 2.3.1 and 2.3.2), or the registers are configured by the application (see 2.3.3).
2.3.1 Use VX1000 defaults
When using “VX1000 defaults”, the VX1000 hardware configures the multiplexer and clock divider in the target in an educated guess approach. Typically, clock sources are selected that are expected to be in use in the target, like clocks for cores or the system clock. The VX1000 uses the divider, that results in the maximum possible Trace_Clk frequency supported by the controller. Because the controller and especially the clock tree can be configured in different ways, this setting will not always lead to the expected results. Use the “Last detected frequency” information in VXconfig to verify the resulting frequency. If the trace clock is not as expected, see the following sections.
2.3.2 VXconfig settings

If actual values are provided in VXconfig, the VX1000 hardware will set TPIU Clock MUX and TPIU Clock Divider without the need to modify the ECU software. This allows an easy probing of different settings. Use the “Last detected frequency” to verify that the resulting frequency meets your expectations.
2.3.3 Use ECU settings

While with the previous configuration modes the VX1000 hardware actively configures the TPIU Clock in the target, the VX1000 can also be put in passive mode by selecting “Use ECU Settings”. In this case, the ECU software must configure the complete Trace Pin interface, as the VX1000 will not modify the clock configuration.

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VX1000 ARM TPIU Trace
Please note that the trace sources like STM500, ETM and ITM are still configured by the VX1000 and must not be accessed by the ECU application. Tip: To verify your settings, boot the target system with the VX1000 disconnected and check with an oscilloscope that the Trace_Clk pin on the target connector is toggling at the expected rate.
2.4 Konfigurace ovladače aplikace VX1000
To use the ARM TPIU trace feature, the VX1000 Application Driver must be included into the Target Controller software. This software is delivered as source code and can be integrated easily. The required configuration options that are needed for the TPIU Trace are listed here. Target controller specific settings are listed in “4 Code Examples for TPIU Configuration” in the “Target Specific Application Driver Configuration” sections //Enables the VX1000 Olda Feature required for data acquisition #define VX1000_OLDA //Activate the memsync measurement method that is required for TPIU measurement #define VX1000_MEMSYNC_TRIGGER_COUNT 1 //Configure the correct Memync Address. See “4. Code Examples for TPIU Configuration” for controller specific values. #define VX1000_MEMSYNC_TRIGGER_PTR ${Target_Specific values}

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VX1000 ARM TPIU Trace

3 Performance considerations
The measurement methods used with the TPIU Trace interface are all copy-based approaches. This means that the data must be copied by the CPU from its original location to a destination where the Trace messages are generated and sent via the TPIU interface. The involved trace protocols also consume some bandwidth of the target interface and must be considered.
Please note that our OLDA copy methods typically consume a CPU runtime of 0,4 % – 5% /
3.1 Target Interface Bandwidth
3.1.1 Due to the number of different setups, the following table provides an overview of actual target interface bandwidth. Bandwidth Examples of STM500

Number of Trace Pins 4 4 4 8 8 8 16 16 16

Trace_CLK Frequency (Mhz)
25 50 80 25 50 80 25 50 80

Bandwidth (Mbyte/s)
7-10 15-21 24-33 15-21 31-42 49-67 31-42 62-84 99-134

3.2 Stalling
All the trace protocols utilizing the TPIU Interface are configured by the VX1000 in such a way that stalling is enabled. This means that no data can get lost due to target interface bandwidth limitations. If the data is copied faster than the interface bandwidth, the CPU is stalled/paused until there is space available on the target interface. The trace paths typically include buffers that help smooth out copy bursts, thereby reducing the likelihood of stalling. Please consult the target reference manual of your controller for details.
As a result, the TPIU interface should be used with the maximum possible frequency and as many trace pins as possible to minimize the negative effects of stalling.

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VX1000 ARM TPIU Trace

4 Kód Přamples for TPIU Configuration
The Pseudo Code examples in the section should give you hints on how to configure the TPIU-Subsystem in preparation for DAQ measurement and calibration use.

4.1 Texas Instruments
The Pseudo Codes examples use names from the TI-SDK which is copyright of Texas Instruments. Please refer to the TI-SDK documentation.

4.1.1:263 XNUMX

4.1.1.1 AM263 TPIU Specification

Maximum number of Trace Pins
16

Maximum frequency (target controller specification)
100 Mhz (TI Datasheet) Tested by VX1000: 125 Mhz (in
laboratory)

Default frequency with option “VXconfig settings”
100 MHz

4.1.1.2 AM263 Trace-Pin configuration

VXconfig TPIU Option
TPIU Clock MUX TPIU Clock Divider

Registrovat jméno
TRCCLKOUT_CLK_SRC_SEL (Address: 0x53200c20) TRCCLKOUT_DIV_VAL (Address: 0x53200c24)

VX1000 Default Value
DPLL_CORE_HSDIV_CLKOUT0: 1 Value in register: 0x111 2 Value in register: 0x111

Additional Hints:
·Pins must be configured with PIN_SLEW_RATE_HIGH
4.1.1.3 AM263 Target Specific Application Driver Configuration VX1000_MEMSYNC_TRIGGER_PTR:
#include <drivers/hw_include/am263x/cslr_soc_baseaddress.h> // CSL_STM_STIM_U_BASE == 0x39000000ul #define VX1000_MEMSYNC_TRIGGER_PTR (CSL_STM_STIM_U_BASE + 0x110)

4.1.1.4 Pseudo-Code

/////////////////////////////////////////////////////////////////////////////////////////////

// Initialisation for parallel trace

// 1.

Device settings. **will be necessary in customer application**

// 1.1. Pin configuration

static Pinmux_PerCfg_t pinMuxTrace[] = {

{ PIN_PR0_PRU1_GPIO19, ( PIN_MODE(4) | PIN_PULL_UP | PIN_SLEW_RATE_HIGH ) }, // TRC_CLK

{ PIN_PR0_PRU1_GPIO18, ( PIN_MODE(4) | PIN_PULL_UP | PIN_SLEW_RATE_HIGH ) }, // TRC_CTL

{ PIN_PR0_PRU1_GPIO8, ( PIN_MODE(4) | PIN_PULL_UP | PIN_SLEW_RATE_HIGH ) }, // TRC_DATA3

{ PIN_PR0_PRU1_GPIO9, ( PIN_MODE(4) | PIN_PULL_UP | PIN_SLEW_RATE_HIGH ) }, // TRC_DATA1

{ PIN_PR0_PRU1_GPIO10, ( PIN_MODE(4) | PIN_PULL_UP | PIN_SLEW_RATE_HIGH ) }, // TRC_DATA2

{ PIN_PR0_PRU1_GPIO5, ( PIN_MODE(4) | PIN_PULL_UP | PIN_SLEW_RATE_HIGH ) }, // TRC_DATA0

{ PIN_PR0_PRU1_GPIO4, ( PIN_MODE(4) | PIN_PULL_UP | PIN_SLEW_RATE_HIGH ) }, // TRC_DATAD5

{ PIN_PR0_PRU1_GPIO6, ( PIN_MODE(4) | PIN_PULL_UP | PIN_SLEW_RATE_HIGH ) }, // TRC_DATAD4

{ PIN_PR0_PRU1_GPIO0, ( PIN_MODE(4) | PIN_PULL_UP | PIN_SLEW_RATE_HIGH ) }, // TRC_DATAD6

{ PIN_PR0_PRU1_GPIO1, ( PIN_MODE(4) | PIN_PULL_UP | PIN_SLEW_RATE_HIGH ) }, // TRC_DATAD7

{ PIN_PR0_PRU1_GPIO2, ( PIN_MODE(4) | PIN_PULL_UP | PIN_SLEW_RATE_HIGH ) }, // TRC_DATAD8

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VX1000 ARM TPIU Trace

{ PIN_PR0_PRU1_GPIO3, ( PIN_MODE(4) | PIN_PULL_UP | PIN_SLEW_RATE_HIGH ) }, // TRC_DATAD9 { PIN_PR0_PRU1_GPIO16, ( PIN_MODE(4) | PIN_PULL_UP | PIN_SLEW_RATE_HIGH ) }, // TRC_DATAD10 { PIN_PR0_PRU1_GPIO15, ( PIN_MODE(4) | PIN_PULL_UP | PIN_SLEW_RATE_HIGH ) }, // TRC_DATAD11 { PIN_PR0_PRU1_GPIO11, ( PIN_MODE(4) | PIN_PULL_UP | PIN_SLEW_RATE_HIGH ) }, // TRC_DATAD12 { PIN_PR0_PRU1_GPIO12, ( PIN_MODE(4) | PIN_PULL_UP | PIN_SLEW_RATE_HIGH ) }, // TRC_DATAD13 { PIN_PR0_PRU1_GPIO13, ( PIN_MODE(4) | PIN_PULL_UP | PIN_SLEW_RATE_HIGH ) }, // TRC_DATAD14 { PIN_PR0_PRU1_GPIO14, ( PIN_MODE(4) | PIN_PULL_UP | PIN_SLEW_RATE_HIGH ) }, // TRC_DATAD15 {PINMUX_END, PINMUX_END} }; Pinmux_config(pinMuxTrace, PINMUX_DOMAIN_ID_MAIN); // // 1.2 Trace Clock configuration // volatile CSL_top_rcmRegs *TOP_RCM = (CSL_top_rcmRegs *) CSL_TOP_RCM_U_BASE; TOP_RCM->LOCK0_KICK0 = 0x01234567; TOP_RCM->LOCK0_KICK1 = 0x0fedcba8; //source: 400 MHz DPLL_CORE_HSDIV_CLKOUT0 TOP_RCM->TRCCLKOUT_CLK_SRC_SEL = 0x111;

//divide by 2 ->200MHz ->100MHz DDR clock (400MByte/s with 16 pins) TOP_RCM->TRCCLKOUT_DIV_VAL = 0x111;

// 2. Multiplexer configurations

Settings for demo hardware **only for using TI eval boards**

// 2.1. MII multiplexor U8 on demoboard AMS263-CC (TMDSCNCD263)

// Trace pins can also be used for MII. AMS263-CC has an Ethernet PHY connected.

// Multiplexor U8 switches the signals between PHY and HSEC connector.

// The multiplexor is controlled by a I2C port expander.

// set config register (command 6) to 6: bit=0 means outputs means output,

//default output value is 1, our mux control should be bit 1<<3

uint8_t txdata[] = { 0x06, 0x06 };

I2C_Transaction i2cx;

I2C_Transaction_init(&i2cx);

i2cx.writeBuf

= txdata;

i2cx.writeCount = sizeof txdata;

i2cx.targetAddress = 0x20;

I2C_transfer(gI2cHandle[0], &i2cx);

// 2.2. GPMC multiplexors U4 and U7 on breakout board TMDSHSECDOCK-AM263

// Trace pins can also be used for GPMC memory interface. TMDSHSECDOCK-AM263 has a PSRAM connected.

// Multiplexors U4 to U7 switches the signals between PSRAM and MIPI60 connector.

// The multiplexors are controlled with GPIO44 (enable) and GPIO47 (select).

// The default state of this mux is “Trace” by external pullups on the breakout board.

// We disable the pins in IOMUX so that the default remains active.

static Pinmux_PerCfg_t pinMuxHsecMuxCtrl[] =

{

{ PIN_EPWM0_B, ( PIN_MODE(7) | PIN_PULL_UP | PIN_PULL_DISABLE | PIN_SLEW_RATE_LOW |

PIN_FORCE_INPUT_DISABLE | PIN_FORCE_OUTPUT_DISABLE ) },

{ PIN_EPWM2_A,

( PIN_MODE(7) | PIN_PULL_UP | PIN_PULL_DISABLE | PIN_SLEW_RATE_LOW |

PIN_FORCE_INPUT_DISABLE | PIN_FORCE_OUTPUT_DISABLE ) },

{PINMUX_END, PINMUX_END}

};

Pinmux_config(pinMuxHsecMuxCtrl, PINMUX_DOMAIN_ID_MAIN);

4.1.2 J6E

4.1.2.5 J6E TPIU Specification

Maximum number of Trace Pins
16

Maximum frequency (target controller specification)
50 MHz (unclear from data sheet, test system
is limited by external components)

Default frequency with option “VXconfig settings”
25 MHz

4.1.2.6 J6E Trace-Pin configuration

VXconfig TPIU Option
TPIU Clock MUX TPIU Clock Divider

Registrovat jméno
cgm_tracedata_cfg, field …_sel (Address: 0x2310003c bits 1:0) cgm_tracedata_cfg, field …_div

VX1000 Default Value
1
8

VX1000 ARM TPIU Trace

(Address: 0x2310003c bits 6:4)

Value in register: 0x00080031

Additional Hints:

· For high clock frequencies, configure the outputs with PORT_DRIVE_STRENGTH_15
4.1.2.7 J6E Target Specific Application Driver Configuration VX1000_MEMSYNC_TRIGGER_PTR // #define VX1000_MEMSYNC_TRIGGER_PTR <user defined>
For this chip, VX1000 uses ETM trace and can work with any arbitrary 16 byte block of writeable address space (8 byte aligned), which is used exclusively by the application driver.

If you do not define VX1000_MEMSYNC_TRIGGER_PTR, this block is automatically allocated within the gVX1000 memory range.

It may be possible to improve measurement throughput by defining VX1000_MEMSYNC_TRIGGER_PTR and providing a buffer in faster (TCM) or cached memory.

4.1.3 TDA4M/J721E

4.1.3.8 TDA4 TPIU Specification

Maximum number of Trace Pins
16

Maximum frequency (target controller specification)
100 MHz in 3.3 V mode 150 MHz in 1.8 V mode Tested by VX1000: 100 Mhz in 3.3 V
mode (in laboratory)

Default frequency with option “VXconfig settings”
100 MHz

4.1.3.9 TDA4 Trace-Pin configuration
VXconfig TPIU Option
TPIU Clock MUX

Registrovat jméno
–

TPIU Clock Divider

PLL2_HSDIV_CTRL3 (Address: 0x0068208c)

VX1000 Default Value
–
9 Value in register: 0xXXXXXX08
(high bits are not modified)

Additional Hints:
·Access from MCU cores to STM500 goes through the R5-RAT address translation module. The application driver setting VX1000_MEMSYNC_TRIGGER_PTR is an address in the MCU address space and must translate to address 0x0009000110 in MAIN address space (which is a stimulus port of the STM-500 trace unit). In the example, below, the RAT is programmed to use the same address in both domains.
4.1.3.10 TDA4 Target Specific Application Driver Configuration
VX1000_MEMSYNC_TRIGGER_PTR #define VX1000_MEMSYNC_TRIGGER_PTR (0x09000000 + 0x110)

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VX1000 ARM TPIU Trace
4.1.3.11 Pseudo-Code
#define W(a,d) do {*(volatile uint32_t *)(a) = (d); } while(0) #define R(a) (*(volatile uint32_t *)(a))
/* ———————————————————————-PinMux Init ———————————————————————– */
W(0x0011D008, 0x68ef3490); // CTRLMMR_LOCK7_KICK0 -> unlock I/O partition W(0x0011D00C, 0xd172bc5a); // CTRLMMR_LOCK7_KICK1
W(0x0011C158, 0x08190005); // CTRLMMR_PADCONFIG86 TRC_CLK (MUX=5, no PullUp/Down , DRV_STR=3) W(0x0011C15C, 0x08190005); // CTRLMMR_PADCONFIG87 TRC_CTRL W(0x0011C160, 0x08190005); // CTRLMMR_PADCONFIG88 TRC_DATA0 W(0x0011C164, 0x08190005); // CTRLMMR_PADCONFIG89 TRC_DATA1 W(0x0011C168, 0x08190005); // CTRLMMR_PADCONFIG90 TRC_DATA2 W(0x0011C16C, 0x08190005); // CTRLMMR_PADCONFIG91 TRC_DATA3 W(0x0011C170, 0x08190005); // CTRLMMR_PADCONFIG92 TRC_DATA4 W(0x0011C174, 0x08190005); // CTRLMMR_PADCONFIG93 TRC_DATA5 W(0x0011C178, 0x08190005); // CTRLMMR_PADCONFIG94 TRC_DATA6 W(0x0011C17C, 0x08190005); // CTRLMMR_PADCONFIG95 TRC_DATA7 W(0x0011C180, 0x08190005); // CTRLMMR_PADCONFIG96 TRC_DATA8 W(0x0011C184, 0x08190005); // CTRLMMR_PADCONFIG97 TRC_DATA9 W(0x0011C188, 0x08190005); // CTRLMMR_PADCONFIG98 TRC_DATA10 W(0x0011C18C, 0x08190005); // CTRLMMR_PADCONFIG99 TRC_DATA11 W(0x0011C190, 0x08190005); // CTRLMMR_PADCONFIG100 TRC_DATA12 W(0x0011C194, 0x08190005); // CTRLMMR_PADCONFIG101 TRC_DATA13 W(0x0011C198, 0x08190005); // CTRLMMR_PADCONFIG102 TRC_DATA14 W(0x0011C19C, 0x08190005); // CTRLMMR_PADCONFIG103 TRC_DATA15
/* ———————————————————————-Trace Clock Init ———————————————————————– */
// trace clock is MainPLL2 (perif 1 pll) HSDIV3 // set TRC_CLK frequency to 900 MHz / n #define SET_TRC_CLK_DIV(n) W(0x68208C, 0x8000 | ((n) – 1)) SET_TRC_CLK_DIV(9); // 100 MHz at pins
/* ———————————————————————-Configure R5-RAT to gain access to STM module ———————————————————————– */
W(0x40F90024, 0x09000000); // remap to this address in MCU domain W(0x40F90028, 0x09000000); // STM stimulus base address in MAIN domain W(0x40F9002C, 0x00000000); // high part of address in MAIN domain W(0x40F90020, 0x80000018); //

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VX1000 ARM TPIU Trace
5 VX1000 hardware adaptation
The hardware connection is driven by the number of pins, used trace frequency and the used VX1000 hardware. In the following section, possible target controller connectors are explained alongside a description how a setup with the VX1000 can look like. Available VX1000 adapter and Evalboard Evaluation Kit Heads (EEKHeads) are described, and possible use cases are explained.
5.1 svtage úrovně
The TPIU Interface cannot be used standalone but an additional target interface like SWD or JTAG is required for write accesses to the target. In some situations, the voltage levels of the SWD/JTAG interface and the TPIU pins differ because different banks of the target controller are used, and different I/O banks may have different voltage levels. Setups that can cope with different voltage levels are explicitly highlighted.
5.2 Flat Ribbon cables
Many setups are designed in a way that flat ribbon cables can be used. This ensures an easy, flexible and cheap way connecting the VX1000 POD with the evaluation board/ECU. The maximum frequency allowing stable communication is limited to 100 Mhz. Even though flat ribbon cables can easily be made at any desired length, they should always be kept as short as possible to avoid interference.

Flex-Ribbon cables mostly are symmetrical meaning that both ends have the same number of pins/cables. An asymmetrical usage is also possible meaning that one side has more pins connected as the other side. This allows the flexible adaptation of e.g. a 44-pin connector to a 20-pin connector.
5.3 Customized Flex PCB
For projects in which the flat ribbon cables do not suffice, Vector provides a development service to design and manufacture customized Flex-PCBs to meet the project requirements.

Kontaktní informace: www.vector.com nebo +49-711-80 670-0

VX1000 ARM TPIU Trace

5.4 Typical connector used for TPIU Trace
To mark Pins with special meaning these colors are used
Color and Meaning GND Ground Key Not Used
Reference Voltages

5.4.1 ARM Coresight 20
Link to ARM specification: https://developer.arm.com/documentation/100893/1-0/Target-interface-
connectors/CoreSight-20-connector

Maximum number of Trace Pins
4

Support for different Voltage Levels for
JTAG/SWD and TPIU No

In vehicle usage possible Yes

Komentář

CoreSight 20 Pin connector

Pin CoreSight 20 connector

VTREF GND GND Key GND GND* GND* GND GND GND

TMS/SWDIO

TCK/SWDCLK

TDO/SWO

TDI

nRESET

TRACECK

SLEDOVÁNO0

SLEDOVÁNO1

SLEDOVÁNO2

SLEDOVÁNO3

Figure 2: Pin assignment of Coresight 20 Connector

5.4.2 ARM Mictor 38
Link to ARM specification: https://developer.arm.com/documentation/100893/1-0/Target-interfaceconnectors/Mictor-38-connector

Maximum number of Trace
Špendlíky 16

Support for different Voltage Levels for JTAG/SWD and TPIU
YES TRACE_VTREF -> Voltage Level TPIU DEBUG_VTREF -> Voltage Level JTAG/SWD

In vehicle usage possible
Ano

Komentář

Kontaktní informace: www.vector.com nebo +49-711-80 670-0

VX1000 ARM TPIU Trace

Mictor38 connector Nc Nc GND DBGRQ nSRST TDO/SWO RTCK TCK/SWDCLK TMS/SWDIO TDI nTRST TRACEDATA15 TRACEDATA14 TRACEDATA13 TRACEDATA12 TRACEDATA11 TRACEDATA10 TRACEDATA9 TRACEDATA8

Pin Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

Mictor 38 connector nc nc TRACECLK DBGACK EXTTRIG TRACE_VTREF DEBUG_VTREF TRACEDATA7 TRACEDATA6 TRACEDATA5 TRACEDATA4 TRACEDATA3 TRACEDATA2 TRACEDATA1 “0” “0” “1” TRACECTL TRACEDATA0

Figure 3: Pin assignment of Coresight Mictor 38

Signals not used by the VX1000:
· DBGRQ · DBGACK · EXTTRIG · RTCK · TRACECTL

5.4.3 ARM MIPI60
Link to ARM specification: https://developer.arm.com/documentation/100893/1-0/Target-interfaceconnectors/MIPI-60-connector

Maximum number of Trace Pins 32

Support for different Voltage Levels for JTAG/SWD and TPIU
YES TRACE_VTREF -> Voltage Level TPIU DEBUG_VTREF -> Voltage Level JTAG/SWD

In vehicle usage possible Yes

Komentář
VX1000 supports up to 16 Trace pins

Kontaktní informace: www.vector.com nebo +49-711-80 670-0

VX1000 ARM TPIU Trace

MIPI 60 connector DEBUG_VTREF TCK/SWDCLK TDI RTCK nTRST DBGACK TRRACECLK GND TRACECTL TRACEDATA0 TRACEDATA1 TRACEDATA2 TRACEDATA3 TRACEDATA4 TRACEDATA5 TRACEDATA6 TRACEDATA7 TRACEDATA8 TRACEDATA9 TRACEDATA10 TRACEDATA11 TRACEDATA12 TRACEDATA13 TRACEDATA14 TRACEDATA15 TRACEDATA16 TRACEDATA17 TRACEDATA18 GND Reserved

Pin Pin MIPI 60 connector

TMS/SWDIO

TDO/SWO

nSRST

nTRST_PD

10 DBGRQ

11 12 TRACE_VTREF

13 14 rezervováno

15 16 GND

17 18 TRACEDATA19

19 20 TRACEDATA20

21 22 TRACEDATA21

23 24 TRACEDATA22

25 26 TRACEDATA23

27 28 TRACEDATA24

29 30 TRACEDATA25

31 32 TRACEDATA26

33 34 TRACEDATA27

35 36 TRACEDATA28

37 38 TRACEDATA29

39 40 TRACEDATA30

41 42 TRACEDATA31

43 44 rezervováno

45 46 rezervováno

47 48 rezervováno

49 50 rezervováno

51 52 rezervováno

53 54 rezervováno

55 56 rezervováno

57 58 GND

59 60 rezervováno

Figure 4: Pin assignment of MIPI60

5.4.4 Vector “Coresight 44”

Maximum

Support for different Voltage

In vehicle usage

Komentář

number of Trace Pins

Levels for JTAG/SWD and TPIU

možné

ANO

Ano

VREF_Trace -> Voltage Level TPIU

VTREF -> Voltage Level JTAG/SWD

The Coresight 44 connector is a Vector-defined connector. This connector is used as Target Interface Connector

on the relevant EEK-Heads and PODs.

16 Pin Trace Vtref GND GND Key GND

PIN PIN

16 Pin Trace TMS/SWDIO TCK/SWCLK TDO/SWO TDI nRESET

Kontaktní informace: www.vector.com nebo +49-711-80 670-0

VX1000 ARM TPIU Trace

GND/PWR GND/PWR GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND/Vref-Trace

11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34. 35 36 37 38 39 40 41 42

Figure 5: Pin assignment of Pin Coresight 44

TRACECLK TRACED0 TRACED1 TRACED2 TRACED3 TRACED4 TRACED5 TRACED6 TRACED7 TRACED8 TRACED9 TRACED10 TRACED11 TRACED12 TRACED13 TRACED14 TRACED15

5.5 Vector Adapter
Vector provides adapters for the most important target connectors to simplify the usage of the TPIU Interface in combination with the VX1000.
5.5.1 VX1940.10: Mipi 60 Adapter

Coresight 44 (POD side)

MIPI 60 (ECU side)

Kontaktní informace: www.vector.com nebo +49-711-80 670-0

5.5.2 VX1940.11: Mictor 38 Adapter

VX1000 ARM TPIU Trace

Coresight 44 (POD side)

Mictor 38 (ECU side)

5.6 Vector EEK Heads
5.6.1 VX1902.09 EEK Head
The hardware adaptation for the TPIU/Trace interface is typically realized via the VX1902.09 Head.

Coresight 44

Vector-proprietary POD Connector

5.7 Vector Flex Adapter
The connection between the POD and the EEK Heads is realized with a Flex Adapter VX1901.01.

Kontaktní informace: www.vector.com nebo +49-711-80 670-0

VX1000 ARM TPIU Trace

5.8 Possible TPIU Setups 5.8.1 Setups for VX1453
Note The VX1453 POD supports TPIU trace from hardware revision 7.0 onwards.

5.8.1.12 Coresight 20 Setup

Maximum number of Trace Pins
4

Support for different Voltage Levels for
JTAG/SWD and TPIU No

Asymmetric Flat Ribbon cable 20:44 Pin

HSSL/HSSL2

Coresight 20 VX1902.09B VX1901.01

VX1453

VX1135/VX1161

5.8.1.13 Mictor 38 Setup Flat Ribbon Cable

Support number of TPIU Trace Pins
4,8,16

Support for different Voltage Levels for Jtag/SWD and TPIU Yes

Flat Ribbon cable 44:44 Pin

HSSL/HSSL2

Mictor 38 VX1940.11 VX1902.09B VX1901.01 VX1453

VX1135/VX1161

Kontaktní informace: www.vector.com nebo +49-711-80 670-0

VX1000 ARM TPIU Trace

5.8.1.14 MIPI 60 Setup Flat Ribbon

Support number of TPIU Trace Pins
4,8,16

Support for different Voltage Levels for Jtag/SWD and TPIU Yes

Flat Ribbon cable 44:44 Pin

HSSL/HSSL 2

MIPI 60 VX1940.10 VX1902.09B VX1901.01 VX1453

5.8.1.15 Customized FlexPCB Setups

Support number of TPIU Trace Pins
4,8,16

Support for different Voltage Levels for Jtag/SWD and TPIU Yes

VX1135/VX1161

HSSL/HSSL2

Mictor 38/ MIPI60/ Coresight 20/ Coresight44

Customized Flex-PCB

VX1453
(+ EEK

VX1135/VX1161

6 Kontakty
Úplný seznam všech poboček a adres společnosti Vector po celém světě naleznete na adrese http://vector.com/contact/.

Kontaktní informace: www.vector.com nebo +49-711-80 670-0

Dokumenty / zdroje

VECTOR VX1000 ARM TPIU Trace Microcontroller [pdfNávod k obsluze
VX1000, VX1000 ARM TPIU Trace Microcontroller, ARM TPIU Trace Microcontroller, Trace Microcontroller, Microcontroller

Reference

Uživatelská příručka

Návod k obsluze mikrokontroléru VECTOR VX1000 ARM TPIU Trace

Trasovací mikrokontrolér VX1000 ARM TPIU

Specifikace:

Informace o produktu:

TPIU Trace Overview:

TPIU Trace Protocols:

Návod k použití produktu:

1. Setting up TPIU Trace:

2. Pin Configuration:

3. Multiplexer Configurations:

4. Trace Clock Configuration:

FAQ:

Q: Where can I find code examples for pin configuration for
different target controllers?

Q: How do I configure the Trace Clock frequency?

Dokumenty / zdroje

Reference

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