Uživatelská příručka k sadě MICROCHIP AN5978 Polar Fire FPGA Splash Kit

The DATA_HANDLE_0 block interfaces with the GUI to select PRBS
or waveform input.
The selected input is forwarded to the DATA_GENERATOR_0 block
for data generation.

The data is sent to the CoreJESD204BTX IP core for transmitter
funkcí.
The transmitted data is received by the CoreJESD204BRX IP core
for receiver functions.

Data errors or link errors selected on the GUI are generated by
the error generator block.

FAQ

Q: What software versions are needed to create the reference
design?

A: For all software versions required, refer to the readme.txt
file uvedeno v návrhu files.

Otázka: Jak mohu view the selected input on the GUI?

A: The GUI displays the selected input when connected to the
CoreJESD204BRX IP core.

“`

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PolarFire FPGA Splash Kit JESD204B Standalone Interface Application Note
AN5978
Úvod (Zeptejte se)
This document describes how to run the JESD204B standalone demo design on the PolarFire® Splash Board
using the JESD204B Standalone Demo GUI application. The GUI application is packaged along with the design files. The demo design is a reference design built using the PolarFire high-speed transceiver blocks and the CoreJESD204BTX and CoreJESD204BRX IP cores. It operates in Loopback mode by sending the CoreJESD204BTX data to the CoreJESD204BRX IP core through the transceiver lanes, which are looped back on the board. This loopback setup facilitates a standalone JESD interface demo that does not require Analog-to-Digital Converter (ADC) or Digital-to-Analog Converters (DAC).
Microchip PolarFire devices have embedded, high-speed transceiver blocks that can handle data rates ranging from 250 Mbps to 12.5 Gbps. The transceiver (PF_XCVR) module integrates several functional blocks to support multiple high-speed serial protocols within the FPGA. JESD204B is a high-speed serial interface standard for data converters developed by the JEDEC committee. The JESD204B standard reduces the number of data inputs and outputs between the high-speed data converters and receivers.
Microchip provides CoreJESD204BTX and CoreJESD204BRX IP cores that implement the transmitter and receiver interfaces of the JESD204B standard. These IP cores are easy to integrate with JESD204B- based data converters to develop high-bandwidth applications such as wireless infrastructure transceivers, software-defined radios, medical imaging systems, and radar and secure communications. These IP cores support link widths from x1 to x4, and link rates from 250 Mbps to 12.5 Gbps per lane using subclass 0, 1 and 2.
For more information about the JESD204B interface design implementation, and all the necessary blocks and IP
cores instantiated in Libero® SoC, see Demo Design.
The JESD204B standalone interface design can be programmed using any of the following options: · Using the .job file: Chcete-li naprogramovat zařízení pomocí .job file dodávané spolu s designem files, viz
Programming the Device Using FlashPro Express. · Using Libero SoC: To program the device using Libero SoC, see Running the Demo Design. Use this option
when the demo design is modified.

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AN5978
Obsah
Introduction……………………………………………………………………………………………………………………………………………………… 1 1. Design Requirements………………………………………………………………………………………………………………………………… 3 2. Prerequisites……………………………………………………………………………………………………………………………………………… 4 3. Demo Design………………………………………………………………………………………………………………………………………………5
3.1. Design Implementation…………………………………………………………………………………………………………………….5 3.2. IP Configuration………………………………………………………………………………………………………………………………. 6 4. Clocking Structure……………………………………………………………………………………………………………………………………. 10 5. Reset Structure………………………………………………………………………………………………………………………………………… 11
6. Simulating the PolarFire® JESD204B Design……………………………………………………………………………………………… 12
6.1. Simulation Flow………………………………………………………………………………………………………………………………13 7. Setting Up the Demo……………………………………………………………………………………………………………………………….. 15 8. Programming the Device Using FlashPro Express…………………………………………………………………………………….. 17 9. Running the Demo…………………………………………………………………………………………………………………………………… 19
9.1. Installing the GUI…………………………………………………………………………………………………………………………….19 9.2. Running the Demo Design………………………………………………………………………………………………………………19 10. Appendix A: References…………………………………………………………………………………………………………………………….25 11. Appendix B: Running the TCL Script…………………………………………………………………………………………………………. 26 12. Revision History……………………………………………………………………………………………………………………………………….. 27 Microchip FPGA Support………………………………………………………………………………………………………………………………….28 Microchip Information……………………………………………………………………………………………………………………………………. 28 Trademarks……………………………………………………………………………………………………………………………………………… 28 Legal Notice………………………………………………………………………………………………………………………………………………28 Microchip Devices Code Protection Feature………………………………………………………………………………………………29

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AN5978 Design Requirements

Požadavky na design (Zeptejte se)

The following table lists the resources required to run the demo.

Tabulka 1-1. Požadavky na design
Requirement Operating System
Železářské zboží
PolarFire® Splash Kit with MPF300T-1FCG484E device
Software FlashPro Express GUI executable (provided with the design files)
Systém na čipu Libero®

Verze
Windows® 10 and 11
Rev 2 or later
For all the software versions needed to create this reference design, see readme.txt file uvedeno v návrhu files.

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AN5978 Předpoklady

Předpoklady (Zeptejte se)

Než začnete, proveďte následující kroky:
· Download and install Libero® SoC (as indicated in the website for this design) on the host PC
from Libero SoC Documentation.

· Stáhněte si demo design files from www.microchip.com/en-us/application-notes/an5978.

· Install the GUI application by running the setup.exe file k dispozici v designu files folder: <$Design_Files_Directory>/mpf_an5978_df/GUI
At the end of the installation, you may be prompted to download and install the FPGA_GUI_Pack, if it is not already available on your system.

· Alternatively, you can manually download and install the Microchip FPGA_GUI_Pack.

Important:A Libero® Gold license is required to evaluate your designs using the PolarFire® Splash Kit.

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Demo design AN5978

Demo design (Zeptejte se)

The PolarFire® JESD204B demo design is developed to interface JESD204B-compliant data
converters with PolarFire devices. The design functions as follows:

1. The DATA_HANDLE_0 block interfaces with the GUI. The GUI enables the selection of either PRBS or waveform input.

2. The DATA_HANDLE_0 block forwards the input selection to the DATA_GENERATOR_0 block, which generates and sends the corresponding input data to the CoreJESD204BTX IP core.

3. The CoreJESD204BTX IP core performs JESD204B transmitter functions based on the configuration and transmits the data to the PF_XCVR (transceiver) IP core.

4. The encoded data is received by the CoreJESD204BRX IP core because the TX and RX lanes of the PF_XCVR block are looped back.

5. The CoreJESD204BRX IP core performs JESD204B receiver functions based on the configuration and transmits the data to the GUI for viewing the selected input.

Important:When a data error or link error is selected on the GUI, the error generator block generates that error and displays it on the GUI.

The following figure shows the hardware implementation of the JESD204B interface demo. Figure 3-1. Hardware Implementation Block Diagram

JESD204B_GUI

Tkanina

DATA HANDLE

Generátor dat

Core JESD204BTX

PRBS Checker

LINK ERROR GENERATOR
Core JESD204BRX

Lane 0 TX XCVR
Lane 0 RX

TXD_P, TXD_N RXD_P, RXD_N

PF_TPSRAM (Data Buffer)

PF_TPSRAM (Status Buffer)

LED_DEBUG_BLK

3.1.

Design Implementation (Ask a Question)
The following figure shows the Libero® design implementation of the JESD204B interface demo.

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Figure 3-2. JESD204B Interface Design

Demo design AN5978

The following table lists the important input and output signals of the design.

Tabulka 3-1. Vstupní a výstupní signály
Signal Input Signals LANE0_RXD_P and LANE0_RXD_N ARST_N RX REF_CLK_PAD_P_0 and REF_CLK_PAD_N_0 SEL_IN[3:0] Output Signals LANE0_TXD_P and LANE0_TXD_N LED_OUT[7:0] TX

Popis
Transceiver receiver differential inputs External reset obtained from push button switch on board Receiver of UART interface Differential reference clock obtained from the on-board 125 MHz oscillator
Signal mapped to DIPs 1, 2, 3 and 4 of SW8 dip slide switch used to debug the status and errors
Transceiver transmitter differential outputs Signal that indicates whether link is up or down Transmitter of UART interface

3.2.

IP Configuration (Ask a Question)
The hardware design for the JESD204B interface includes the following blocks.

3.2.1.

Data Handle (Ask a Question)
The data handle (DATA_HANDLE_0) block receives the input data selection and link or data error generation information from the GUI. This block also sends the data output received from the CoreJESD204BRX core and the data or link status error to the GUI for viewIng.

3.2.2.

Data Generator (Ask a Question)
The data generator has a PRBS generator and a waveform generator. The PRBS generator generates PRBS7, PRBS15, PRBS23 and PRBS31 patterns. An error insertion mode implemented in the PRBS generator inserts an error into the PRBS sequence. The waveform generator generates sine, sawtooth, triangle and square waveforms. The data generator feeds a 64-bit test pattern to the JESD204BTX core, which subsequently transmits the data to the transceiver.

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3.2.3.

Demo design AN5978
PF_TPSRAM (Ask a Question)
There are two instances of PF_TPSRAM blocks, the PF_TPSRAM_C0 block stores the JESD204B link status before sending it to the GUI. The PF_TPSRAM_C1 block stores the data received from the CoreJESD204BRX before sending the data to the GUI.

3.2.4.

Error Generator (Ask a Question)
The error generator block (ERR_GEN_0) generates link errors by sending random data between CoreJESD204BTX and PF_XCVR when link error generation is selected in the GUI.

3.2.5.

PRBS_checker (Ask a Question)
The data checker receives 64-bit data from the CoreJESD204BRX IP core and checks whether the received data is correct. It generates an error count and a status signal, which are transmitted to the GUI for status indication. The data checker exclusively checks the PRBS sequences generated by the data generator.

3.2.6.

LED Debug (Ask a Question)
The LED debug block (LED_DEBUG_BLK_0) debugs the JESD204B link status and other errors. When the link is up, LEDs 1, 2, 3, 4, 5 and 6 glow, while LEDs 7 and 8 do not glow (with DIP 1, 2, 3 and 4 are set to low on the SW8 dip slide switch).

3.2.7.

Init_monitor (Ask a Question)
When the DEVICE_INIT_DONE signal from Init_monitor block goes high, the transceiver is completely configured. This signal is anded with ARST_N signal to get proper reset signal for the design.

3.2.8.

CORERESET_PF (Ask a Question)
CoreReset_PF synchronizes resets to the user-specified clock domain. This ensures that while the assertion is asynchronous, the negation is synchronous with the clock.

3.2.9.

CoreJESD204BTX (Ask a Question)
CoreJESD204BTX is the transmitter interface of the JEDEC JESD204B standard. For this demo design,
this IP core is configured in Libero®, as shown in the following figure.

Figure 3-3. CoreJESD204BTX Configurator

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For more information about CoreJESD204BTX, see CoreJESD204BTX Handbook.

Demo design AN5978

3.2.10. CoreJESD204BRX (Ask a Question)
CoreJESD204BRX is the receiver interface of the JEDEC JESD204B standard. For this demo design, this
IP core is configured in Libero®, as shown in the following figure.
Poznámka: Komu view the complete configuration, open the configurator of IP from within the design.

Figure 3-4. CoreJESD204BRX Configurator

For more information about CoreJESD204BRX, see CoreJESD204BRX Handbook.

3.2.11.

Transceiver Interface (Ask a Question) The PolarFire® high-speed transceiver (PF_XCVR) is a hard IP block designed to support high-speed
data rates ranging from 250 Mbps to 12.5 Gbps. In this demo, the transceiver block (PF_XCVR) is configured in 8b10b mode with a Clock Data Recovery (CDR) reference clock of 125 MHz to support 5.0 Gbps data rate.

The PolarFire transmit PLL (PF_TX_PLL) provides the reference clock feed to the transceiver. The dedicated reference clock (PF_XCVR_REF_CLK) drives the PF_TX_PLL to generate the desired output clock for the 5.0 Gbps data rate.

Následující obrázek ukazuje konfiguraci rozhraní transceiveru.

Poznámka: Komu view the complete configuration, open the configurator of IP from within the design.

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Figure 3-5. Transceiver Interface Configurator

Demo design AN5978

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AN5978 Clocking Structure

Struktura hodin (Zeptejte se)

In the reference design, there are three clock domains:

· RX_CLK (125 MHz)

· TX_CLK (125 MHz) · FAB_REF_CLK (125 MHz)

The on-board 125-MHz crystal oscillator drives the XCVR reference clock, which provides clock to the DATA_GENERATOR, CoreJESD204BTX, ERR_GEN, CoreJESD204BRX, LED_DEBUG, PRBS_CHECKER, TPSRAM C0 & C1 and DATA_HANDLE.

Important:If there is a change in the data rate or reference clock of the transceiver, you must reconfigure COREUART.

The following figure shows the clocking structure. Figure 4-1. Clocking Structure

Clock Domain 1
On-Board 125 MHz Crystal Oscillator

DATA_GENERATOR

LANE0_TX_CLK_R

PF_XCVR_REF_CLK
REF_CLK
PF_TX_PLL
CLKS_TO_XCVR
PF_XCVR

CDR CLK

FAB_REF_CLK

ČÍST

DATA_HANDLE

TPSRAM 0 and 1

LANE0_RX_CLK_R WRITE

ERR_GEN

COREJESD204BTX

COREJESD204BRX

TPSRAM 0 and 1

PRBS_CHECKER

LED_DEBUG_BLK

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AN5978 Reset Structure

Obnovit strukturu (položit otázku)

The DEVICE_INIT_DONE and external reset signal ARST_N are mapped to pin N4 on the Splash Kit. These signals initiate the system reset (FABRIC_RESET_N) through the res_syn_0 block.

The FABRIC_RESET_N signal from the res_syn_0 block provides a direct reset to the following modules:
· CoreJESD204BRX

· CoreJESD204BTX · PF_XCVR (LANE0_PMA_ARST_N)

Additionally, FABRIC_RESET_N is connected to the reset synchronizer block, which distributes synchronized reset signals to the following functional blocks:
· prbs_checker

· DATA_HANDLE · DATA_GENERATOR

· ERR_GEN · LED_DEBUG_BLK

RX_RESET_N output from the CoreJESD204BRX module supplies reset signals to: · LANE0_PCS_ARST_N input of the PF_XCVR_0 module · LED_DEBUG block (EPCS_0_RX_RESET_N)

Následující obrázek ukazuje strukturu resetování.

Obrázek 5-1. Obnovit strukturu

PF_INIT_MONITOR

DEVICE_INIT_DONE

Reset_syn_0

ARST_N (N4)

FABRIC_RESET_N

reset_synchronizer

CoreJESD204BTX

PF_XCVR

CoreJESD204BRX

prbs_checker

DATA_HANDLE DATA_GENERATOR

ERR_GEN

LED_DEBUG_BLK

RX_RESET_N

PF_XCVR

EPCS_0_RX_RESET_N
LED_DEBUG_BLK

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AN5978 Simulating the PolarFire® JESD204B Design

Simulating the PolarFire® JESD204B Design (Ask a Question)

Chcete-li simulovat návrh, proveďte následující kroky:
1. Start Libero®, and select Project > Tool Profiles….

2. In the Tool Profiles window, select Synthesis and Simulation on the Tools panes and select the latest active installation directory paths for these two tools.

For Simulation, browse the design files folder, create Libero Project using provided TCL scripts, and click Simulate as highlighted in the Figure 6-2. For more information, see Appendix B: Running the TCL Script.

A testbench is provided to simulate the JESD204B PRBS pattern and waveform selection. The following figure shows the interaction between testbench and the design.

Figure 6-1. Testbench and JESD204B Demo Design Interaction

P_W_SEL PRBS_SEL WAVE_SEL ERR_EN NSYSRESET SYSCLK
TB_DATA_OUT TB_RX_SOMF TB_RX_SOF TB_SYNC_N TB_ALIGNED

JESD204B Top Block (DUT)

Generátor dat
Kontrola dat

Core JESD204BTx
Core JESD204BRx

Lane 0 Tx Transceiver Lane 0 Rx

TB_LINK_CD_ERR

TB_UCC_ERR TB_NIT_ERR TB_DISP_ERR TB_CGS_ERR TB_RX_READY

TB_0_BAD

TB_0_ERROR

Testbench

TXD2P, TXD2N Loopback
RXD2P, RXD2N

The testbench generates the test selection for the PRBS input (PRBS7, PRBS15, PRBS23 and PRBS31) and waveform input (sine wave, sawtooth wave, triangle wave and square wave). It also monitors the JESD204B output status signals (SYNC_N, ALIGNED and CGS_ERR) for the verification of JESD204B phases, and PRBS checker output status signals O_BAD and O_ERROR[4:0].
To simulate the design, in the Design Flow tab, double-click Simulate under Verify PreSynthesized Design. The Simulate option is highlighted in the following figure.

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Figure 6-2. Simulating the Design

AN5978 Simulating the PolarFire® JESD204B Design

When the simulation is initiated, simulation tool compiles all the design source files, runs the simulation, and configures the waveform viewer to show the simulation signals.
Note:In certain cases, a prompt may appear asking for the selection of an active stimulus before starting the simulation. To resolve this, navigate to the Stimulus Hierarchy, right-click PF_JESD204B_SA_TOP_TB_8b (top.v) and select Set as Active Stimulus, as shown in the following figure.
Figure 6-3. Set As Active Stimulus

6.1.

Simulation Flow (Ask a Question)
The following steps describe the JESD204B testbench simulation flow: 1. At the start, the NSYSRESET signal resets all of the components. 2. After the transceiver block is initialized, the TB_RX_READY signal is asserted high. 3. The JESD204BRX issues a synchronization request by driving the TB_SYNC_N pin low. 4. The JESD204BRX block checks the k28.5 characters transmitted by the JESD204BTX block. 5. The CGS and ILA phase starts after the TB_SYNC_N signal is asserted high. 6. The testbench checks whether the CGS_ERR signal asserts low or not, and completes the code
group synchronization phase. 7. The JESD204BRX link asserts the TB_SYNC_N signal to high. 8. After the successful completion of the CGS phase, the JESD204BTX block starts the Initial Lane
Alignment (ILA) sequence by transmitting four multi-frames in the following sequence: First frame at TB_TX_SOMF = 0x8 Second frame at TB_TX_SOMF = 0x2 Third frame at TB_TX_SOMF = 0x8

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AN5978 Simulating the PolarFire® JESD204B Design
Fourth frame at TB_TX_SOMF = 0x2 9. The JESD204BRX link starts receiving four multi-frames in the following sequence:
First frame at TB_TX_SOMF = 0x8 Second frame at TB_TX_SOMF = 0x2 Third frame at TB_TX_SOMF = 0x8 Fourth frame at TB_TX_SOMF = 0x2 10. The ILA phase test passes if all JESD204BRX DATA_OUT is properly received with frame alignment. 11. After successful completion of the ILA phase, the JESD204BTX block enters into the data phase. 12. In the data phase, the following data is fed to the JESD204BTX block: PRBS7, PRBS15, PRBS23 and PRBS31 using the PRBS generator. 13. Sine, Square, Saw and triangular waves are generated from the waveform generator. 14. The PRBS checker checks the received PRBS pattern against the expected PRBS pattern. 15. The waveform output can be viewed in the simulation window on corresponding wave selection as shown in Figure 6-5. 16. If the data checker does not detect any error, the testbench issues a TESTBENCH PASSED message stating that the simulation was successful. If an error is detected, the testbench issues a TESTBENCH FAILED message to indicate that the testbench has failed.
While the simulation is running, you can see the status of the test cases in the Transcript window of ModelSim, as shown in the following figure.
Figure 6-4. Transcript Window

After simulation, the Waveform window displays the simulation waveforms as shown in the following figure.
Note:You may notice some warnings in the log. These appear because UART is not used in the simulation. The simulation is focused only on JESD, while UART and RAM are included for GUI purposes.
Figure 6-5. Simulation Waveform Window

SYNC_N Deassertion

CGS and ILA

PRBS Sequence: PRBS 7, 15, 25, 31

Waveforms: Sine, Square, Sawtooth, Triangle

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AN5978 Nastavení ukázky

Nastavení ukázky (Zeptejte se)

After generating the bitstream, the PolarFire® device must be programmed. To program the

PolarFire device, perform the following steps:

1. Ensure that the jumper settings on the board are same as listed in the following table.

Tabulka 7-1. Nastavení propojky

Popis propojky

J11

Close pin 1 and 2 for programming through the FTDI chip.

Open pin 1 and 2 for programming through an external FlashPro4 or FlashPro5 device.

Default Closed

Jumper to select the core voltage.

Close pin 1 and 2 for 1.05 V.

Open pin 1 and 2 for 1.0 V.

OTEVŘENO

J10

Close pin 1 and 2 for programming through the external SPI flash.

If J10 is open, it allows SPI slave programming using the FTDI chip.

OTEVŘENO

2. Connect the power supply cable to the J2 connector on the board. 3. Connect the USB cable from the host PC to the J1 (FTDI port) on the board. 4. Power On the board using the SW1 slide switch.
When the board is powered up, power supply LEDs 1 to 4 glow. For more information about LEDs on the PolarFire Splash Board, see UG0786: PolarFire FPGA Splash Kit User Guide. 5. In Libero Design Flow tab, double-click Run PROGRAM Action.

Na view odpovídající log file, navigate to Reports tab, right-click Run Program Action and select View Zpráva.

When the device is successfully programmed, a green tick mark appears as shown in the following figure. For information about how to run the JESD204B standalone demo, see Running the Demo.

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Figure 7-1. Device Programming Completed

AN5978 Nastavení ukázky

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AN5978 Programming the Device Using FlashPro Express
8. Programming the Device Using FlashPro Express (Ask a Question)
This section describes how to program the PolarFire® device with the programming job file
pomocí FlashPro Express. Práce file je k dispozici v následujícím provedení files folder location: mpf_an5978_df/Programming_Files/top.job.
To program the device, perform the following steps: 1. On the host PC, launch the FlashPro Express software. 2. To create a new project, click New or New Job Project from FlashPro Express Job from Project
menu. 3. Enter the following in the New Job Project from FlashPro Express Job dialog box:
Programming job file: Klikněte na Procházet a přejděte do umístění, kde se úloha nachází file se nachází a vyberte file. The default location is: mpf_an5978_df/Programming_Files/ top.job.
FlashPro Express job project location: Click Browse and navigate to the FlashPro Express project location.
Figure 8-1. New Job Project from FlashPro Express Job

4. Klepněte na tlačítko OK. Požadované programování file je vybrán a připraven k naprogramování v zařízení.
5. The FlashPro Express window appears, as shown in the following figure. Confirm that a programmer number appears in the Programmer field. If not, confirm the board connections and click Refresh/Rescan Programmers.

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Obrázek 8-2. Programování zařízení

AN5978 Programming the Device Using FlashPro Express

6. Click RUN. When the device is programmed successfully, a RUN PASSED status is displayed as shown in the following figure.
Figure 8-3. FlashPro Express–RUN PASSED

7. Close FlashPro Express or click Exit in the Project tab.

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AN5978 Spuštění ukázky

9.
9.1.
9.2.

Spuštění ukázky (Zeptejte se)
This section describes how to use the JESD204B GUI to run the JESD204B demo on the PolarFire®
Splash Board.
Installing the GUI (Ask a Question)
To run the demo, install the JESD204B GUI. The GUI allows selection of different PRBS test patterns as input, and displays the JESD204B status signals and the PRBS status received from the board. The Waveform tab of the GUI displays the output waveforms received from the board for each waveform selected as input.
To install the GUI, perform the following steps: 1. Install the JESD204B_GUI application (setup.exe) from the following design files folder:
mpf_an5978_df/GUI.
2. To start the GUI application, double-click the JESD204B_GUI application from the installation directory.
Running the Demo Design (Ask a Question)
To run the JESD204B demo, perform the following steps:
1. Connect the jumpers and set up the PolarFire® Splash Board as described in steps 1 to 4 of
Setting Up the Demo.
2. In Device Manager on the host PC, note the COM port associated with the USB serial converter C. To determine the COM port, check the Location field in the properties of each COM port.
3. On the Start menu of the host PC, click JESD204B_GUI.
4. From the list of COM ports, select the COM port identified in the step 2, and click Connect, as shown in the following figure.
Figure 9-1. COM Port Selection

DS00005978A – 19

Important:Port numbers may vary. In this example, COM port 32 is the correct port to select.

AN5978 Spuštění ukázky

After successful connection, the Host Connection indicator turns green, as shown in the following figure.
Figure 9-2. Successful Host Connection

The following table lists the status signals displayed in the JESD204B GUI.

Table 9-1. Status Signals in JESD204B GUI

Signál

Popis

Host Connection Shows the UART communication status.

Stav odkazu

Shows the communication link status between TX and RX.

SYNC_N

Indicates the JESD204B status.

ZAROVNANÝ

Indicates that all transceiver lanes are aligned.

RX VALID

Indicates that RX data is valid. In 8b10b mode, indicates that comma alignment has occurred and the CDR is locked.

PRBS Status

Indicates PRBS error.

Počet chyb

Provides the number of errors that occurred during PRBS check

CGS_ERR

Indicates a code group synchronization error.

NIT_ERR

Indicates a “not in table” error.

DISP_ERR

Indicates a disparity error.

LINK_CD_ERR Indicates a link configuration data mismatch.

UCC_ERR

Indicates an “unexpected control character” error.

5. From the Input Selection list, select the pattern to be transmitted, and click START, as shown in the following figure.

DS00005978A – 20

Figure 9-3. Pattern Selection

AN5978 Spuštění ukázky

The selected pattern is sent over the serial transmit link and received by CoreJESD204BRX, which checks for errors. At any time, the JESD204B status can be monitored using the status signals on the GUI, as shown in the following figure.
Figure 9-4. Link Status and JESD204B Status

6. To generate an error in the PRBS data, click Generate Data Error. The PRBS Status indicator turns red, and the Error Count field displays the number of errors, as shown in the following figure.

DS00005978A – 21

Figure 9-5. Data Error

AN5978 Spuštění ukázky

7. Click Clear Error to clear the errors in the PRBS data and reset the PRBS status. The PRBS Status indicator turns green, and the Error Count changes to 0, as shown in the following figure.
Figure 9-6. Data Error Cleared

8. To generate a link error between CoreJESD204BTX and the transceiver lane, click Generate Link Error.
The Link Status, SYNC_N, ALIGNED, RX VALID, DISP_ERR and CGS_ERROR indicators turn red, as shown in the following figure.

DS00005978A – 22

Figure 9-7. Link Error

AN5978 Spuštění ukázky

9. To clear the link error, click Clear Error. The status indicators turn green, as shown in the following figure.
Figure 9-8. Clear Link Error

10. To change the pattern, select Triangle from the Input Selection list. The selected pattern is sent over the serial transmit link and received by CoreJESD204BRX. At any time, the JESD204B status can be monitored using the status signals on the GUI.
11. Komu view the waveform received from CoreJESD204BRX, click the Waveform tab, as shown in the following figure.

DS00005978A – 23

Figure 9-9. Triangle Waveform

AN5978 Spuštění ukázky

12. To end the demo, click Stop and close the GUI.

DS00005978A – 24

AN5978 Appendix A: References

10.

Appendix A: References (Ask a Question)
This section lists documents that provide more information about the JESD204B standard and IP cores used in the demo design.
· For information about the JESD204B interface standard, visit the JEDEC webmísto.
· For information about PolarFire transceiver blocks, PF_TX_PLL and PF_XCVR_REF_CLK, see PolarFire Family Transceiver User Guide.
· For more information about PF_TPSRAM (PF Micro SRAM), see PolarFire Family Fabric User Guide.
· For more information about CoreJESD204BTX, see CoreJESD204BTX Handbook.
· For more information about CoreJESD204BRX, see CoreJESD204BRX Handbook.
· For more information about Libero, ModelSim and Synplify, see the Microchip Libero SoC webstrana.

DS00005978A – 25

AN5978 Appendix B: Running the TCL Script

11.

Appendix B: Running the TCL Script (Ask a Question)
V návrhu jsou uvedeny skripty TCL files složka v adresáři HW. V případě potřeby lze tok návrhu reprodukovat od implementace návrhu až po vytvoření zakázky file. To run the TCL, perform the following steps:
1. Launch the Libero® software.
2. Select Project > Execute Script….
3. Click Browse and select script.tcl from the downloaded HW directory.
4. Click Run.
After successful execution of TCL script, Libero project is created within HW directory. For more information about TCL scripts, see mpf_an5978_df/HW/TCL_Script_readme.txt.
For more details on TCL commands, see TCL Commands Reference Guide. For any queries encountered when running the TCL script, contact Technical Support.

DS00005978A – 26

AN5978 Historie revizí

12.

Historie revizí (Zeptejte se)
Historie revizí popisuje změny, které byly v dokumentu implementovány. Změny jsou uvedeny podle revizí, počínaje aktuální publikací.

Revize A

Datum 08. 2025

Description The following is the list of changes made in the revision A of the document: · The document was migrated to the Microchip template. · The document number was updated from 50200796 to DS00005978. · The document ID was updated from DG0796 to AN5978.

3.0

—

This document is updated with respect to Libero® SoC PolarFire v2.2 release.

2.0

—

This document is updated with respect to Libero SoC PolarFire v2.1 release.

1.0

—

První zveřejnění tohoto dokumentu.

DS00005978A – 27

AN5978

Podpora Microchip FPGA
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Kontaktujte centrum technické podpory prostřednictvím webna adrese www.microchip.com/support. Uveďte číslo dílu FPGA zařízení, vyberte vhodnou kategorii pouzdra a nahrajte design files při vytváření případu technické podpory.
Obraťte se na zákaznický servis pro netechnickou podporu produktu, jako je cena produktu, aktualizace produktu, informace o aktualizaci, stav objednávky a autorizace.
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ISBN: 979-8-3371-1709-6
Právní upozornění
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TYTO INFORMACE POSKYTUJE SPOLEČNOST MICROCHIP „TAK JAK JSOU“. MICROCHIP NEPOSKYTUJE ŽÁDNÁ PROHLÁŠENÍ ANI ZÁRUKY JAKÉHOKOLI DRUHU, AŤ UŽ VÝSLOVNÉ ČI PŘEDPOKLÁDANÉ, PÍSEMNÉ NEBO ÚSTNÍ, ZÁKONNÉ NEBO JINÉ, TÝKAJÍCÍ SE INFORMACÍ VČETNĚ, ALE NE OMEZENÍ, JAKÝCHKOLI PŘEDPOKLÁDANÝCH ZÁRUK, ZÁRUK NEPORUŠENÍ TNCH OBCHODU KONKRÉTNÍ ÚČEL NEBO ZÁRUKY VZTAHUJÍCÍ SE K JEHO STAVU, KVALITĚ NEBO VÝKONU.
V ŽÁDNÉM PŘÍPADĚ NEBUDE MICROCHIP ODPOVĚDNÁ ZA ŽÁDNÉ NEPŘÍMÉ, ZVLÁŠTNÍ, TRESTNÉ, NÁHODNÉ NEBO NÁSLEDNÉ ZTRÁTY, ŠKODY, NÁKLADY NEBO NÁKLADY JAKÉHOKOLI DRUHU, JAKKOLI SOUVISEJÍCÍ S INFORMACÍ NEBO JEJICH POUŽITÍM, JAKKOLI BY BYLO UVEDENO, JAK BY BYLO ZPŮSOBeno, MOŽNOST NEBO ŠKODY JSOU PŘEDVÍDAJÍCÍ. CELKOVÁ ODPOVĚDNOST SPOLEČNOSTI MICROCHIP ZA VŠECHNY NÁROKY SOUVISEJÍCÍ S INFORMACEMI NEBO JEJICH POUŽITÍM NEPŘEKROČÍ V NEJVYŠŠÍM ROZSAHU POVOLENÉM ZÁKONEM, KTERÉ JSTE ZA INFORMACE ZAPLATILI PŘÍMO SPOLEČNOSTI MICROCHIP.
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DS00005978A – 28

AN5978
Funkce ochrany kódem zařízení Microchip
Všimněte si následujících podrobností o funkci ochrany kódu na produktech Microchip:
· Produkty Microchip splňují specifikace obsažené v jejich konkrétním datovém listu Microchip. · Microchip věří, že jeho rodina produktů je bezpečná, když je používána zamýšleným způsobem, uvnitř
provozní specifikace a za normálních podmínek. · Microchip si cení a agresivně chrání svá práva duševního vlastnictví. Pokusy o porušení
funkce ochrany kódu produktů Microchip jsou přísně zakázány a mohou porušovat zákon Digital Millennium Copyright Act. · Společnost Microchip ani žádný jiný výrobce polovodičů nemůže zaručit bezpečnost svého kódu. Ochrana kódem neznamená, že garantujeme, že produkt je „nerozbitný“. Ochrana kódu se neustále vyvíjí. Společnost Microchip se zavázala neustále zlepšovat funkce ochrany kódu našich produktů.

DS00005978A – 29

Dokumenty / zdroje

MICROCHIP AN5978 Polar Fire FPGA Splash Kit [pdfUživatelská příručka
AN5978 Polar Fire FPGA Splash Kit, AN5978, Polar Fire FPGA Splash Kit, Fire FPGA Splash Kit, FPGA Splash Kit, Splash Kit

Reference

Uživatelská příručka

Uživatelská příručka k sadě MICROCHIP AN5978 Polar Fire FPGA Splash Kit

Sada FPGA pro detekci rozstřiku AN5978 Polar Fire

Informace o produktu

Specifikace

Návod k použití produktu

Požadavky na design

Předpoklady

Demo design

FAQ

Q: What software versions are needed to create the reference
design?

Otázka: Jak mohu view the selected input on the GUI?

Dokumenty / zdroje

Reference

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